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	<title>MRVL</title>
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		<title>Marvell, Microsoft and Oracle Establish OCP Working Group to Standardize Data Center Ha&#8230;</title>
		<link>https://news.x4a.net/marketwire/marvell-microsoft-and-oracle-establish-ocp-working-group-to-standardize-data-center-ha/</link>
		
		<dc:creator><![CDATA[X4A MarketWire]]></dc:creator>
		<pubDate>Tue, 13 Oct 2026 13:25:45 +0000</pubDate>
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					<description><![CDATA[Marvell, Microsoft and Oracle Establish OCP Working Group to Standardize Data Center Hardware Security New Open Compute Project (OCP) working group: Companies form a new working group to standardize on a silicon-based and attested secure integrated hardware security module (HSM) solution for cloud and hyperscale data center infrastructure. Strengthening cloud security: Secure key caching and [&#8230;]]]></description>
										<content:encoded><![CDATA[<p>Marvell, Microsoft and Oracle Establish OCP Working Group to Standardize Data Center Hardware Security</p>
<p>New Open Compute Project (OCP) working group: Companies form a new working group to standardize on a silicon-based and attested secure integrated hardware security module (HSM) solution for cloud and hyperscale data center infrastructure.</p>
<p>Strengthening cloud security: Secure key caching and attestation cryptographic key lifecycle management at the server level will reduce latency, improve scalability and strengthen the security posture of cloud compute workloads.</p>
<p>Open technical specification: Initial draft of technical specification to be released at OCP Global Summit in October 2026, paving the way for broad industry adoption of in-server security for data centers.  | $MRVL $MSFT $ORCL</p>
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		<title>Marvell Bolsters Connectivity Portfolio with New 3.2T Protocol-aware Retimer and Second&#8230;</title>
		<link>https://news.x4a.net/marketwire/marvell-bolsters-connectivity-portfolio-with-new-3-2t-protocol-aware-retimer-and-second/</link>
		
		<dc:creator><![CDATA[X4A MarketWire]]></dc:creator>
		<pubDate>Tue, 13 Oct 2026 13:19:26 +0000</pubDate>
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					<description><![CDATA[Marvell Bolsters Connectivity Portfolio with New 3.2T Protocol-aware Retimer and Second-generation 1.6T AEC DSP Scaling connectivity to 3.2T: Marvell® Alaska® E 3.2T protocol-aware Ethernet, UALink™ and ESUN retimer delivers 16 lanes of 224G PAM4 connectivity for high-bandwidth XPU-to-XPU and XPU-to-switch scale-up architectures. Advancing 200G/lane AECs: Second-generation Alaska A 1.6T AEC DSP moves to the 3nm [&#8230;]]]></description>
										<content:encoded><![CDATA[<p>Marvell Bolsters Connectivity Portfolio with New 3.2T Protocol-aware Retimer and Second-generation 1.6T AEC DSP</p>
<p>Scaling connectivity to 3.2T: Marvell® Alaska® E 3.2T protocol-aware Ethernet, UALink<img src="https://s.w.org/images/core/emoji/17.0.2/72x72/2122.png" alt="™" class="wp-smiley" style="height: 1em; max-height: 1em;" /> and ESUN retimer delivers 16 lanes of 224G PAM4 connectivity for high-bandwidth XPU-to-XPU and XPU-to-switch scale-up architectures.</p>
<p>Advancing 200G/lane AECs: Second-generation Alaska A 1.6T AEC DSP moves to the 3nm node, delivering higher performance and improved power efficiency for 1.6T active electrical cables used across AI racks.</p>
<p>Built for next-generation AI infrastructure: Designed to meet the increasing bandwidth, reach and power-efficiency demands of advanced AI scale-up infrastructure at 224G/lane.</p>
<p>Availability: Alaska E 3.2T protocol-aware retimer and second-generation Alaska A 1.6T are now sampling to customers.  | $MRVL</p>
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		<title>Marvell Unveils Second-generation Structera X, Industry-first Six-channel CXL 3.2 Memory Expanders for AI Inference</title>
		<link>https://news.x4a.net/marketwire/marvell-unveils-second-generation-structera-x-industry-first-six-channel-cxl-3-2-memor/</link>
		
		<dc:creator><![CDATA[X4A MarketWire]]></dc:creator>
		<pubDate>Mon, 12 Oct 2026 17:25:32 +0000</pubDate>
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					<description><![CDATA[Marvell Unveils Second-generation Structera X, Industry-first Six-channel CXL 3.2 Memory Expanders for AI Inference Expanding memory capacity for AI: Second-generation Marvell® Structera™ X 3406 and 3506 CXL 3.2 memory expanders add six DDR4/DDR5 channels (50% more than the prior generation) and PCIe Gen 6 connectivity, supporting up to 9TB of DDR4 or 6TB of DDR5 [&#8230;]]]></description>
										<content:encoded><![CDATA[<p>Marvell Unveils Second-generation Structera X, Industry-first Six-channel CXL 3.2 Memory Expanders for AI Inference</p>
<p>Expanding memory capacity for AI: Second-generation Marvell® Structera<img src="https://s.w.org/images/core/emoji/17.0.2/72x72/2122.png" alt="™" class="wp-smiley" style="height: 1em; max-height: 1em;" /> X 3406 and 3506 CXL 3.2 memory expanders add six DDR4/DDR5 channels (50% more than the prior generation) and PCIe Gen 6 connectivity, supporting up to 9TB of DDR4 or 6TB of DDR5 per controller.</p>
<p>Addresses growing memory demand: Multi-host sharing and inline LZ4 compression deliver up to 2–3x more effective capacity, with up to 40–50% faster time to first token at equivalent context length.</p>
<p>Preview and availability: Demoing at the OCP Summit, the Structera X 3406 and 3506 are expected to sample in Q1 2027, extending the Structera X 2404 and 2504 architecture already shipping to hyperscalers.  | $MRVL</p>
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		<title>Marvell to Showcase Open AI Infrastructure Solutions at OCP Global Summit 2026  &#124; $MRVL</title>
		<link>https://news.x4a.net/marketwire/marvell-to-showcase-open-ai-infrastructure-solutions-at-ocp-global-summit-2026-mrvl/</link>
		
		<dc:creator><![CDATA[X4A MarketWire]]></dc:creator>
		<pubDate>Thu, 08 Oct 2026 16:07:30 +0000</pubDate>
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					<description><![CDATA[Marvell to Showcase Open AI Infrastructure Solutions at OCP Global Summit 2026 &#124; $MRVL]]></description>
										<content:encoded><![CDATA[<p>Marvell to Showcase Open AI Infrastructure Solutions at OCP Global Summit 2026  | $MRVL</p>
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